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A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices

Abstract : In this paper, we present a nanometric layout generation tool for analogue building blocks called devices. We focus on the procedural routing methods inside devices. A device may have one or more folded transistors' fingers merged into at least one stack depending on the chosen layout style. We present two routing methods: intra-stack and inter-stack to ease the routing of the wired segments. Taking advantage of both routing methods, the layout generation tool provides a range of transistor folding to respect the designer-defined constraints (either electrical or physical). Both routing methods are used to generate different layout styles. The layout generation for a differential pair device is illustrated using four layout styles: interdigitated, mirror, 2D common-centroid and M2 modules. Keywords: Migration, Layout Generation, Routing, Stress effects
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Contributor : Stephanie Youssef Connect in order to contact the contributor
Submitted on : Thursday, November 8, 2012 - 3:55:28 PM
Last modification on : Sunday, June 26, 2022 - 9:58:45 AM
Long-term archiving on: : Saturday, February 9, 2013 - 3:50:24 AM


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  • HAL Id : hal-00749930, version 1


Stephanie Youssef, Damien Dupuis, Ramy Iskander, Marie-Minerve Louërat. A Stack-Based Routing Methodology For Nanometric Analogue CMOS Devices. The IEEE Virtual Worldwide Forum For PhD Researchers in Electronic Design Automation, (VW FEDA), Nov 2011, Southampton, United Kingdom. pp.1-6. ⟨hal-00749930⟩



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