Skip to Main content Skip to Navigation
Conference papers

A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation

Abstract : In this paper, a new method for developing smart parameterized generators for analogue devices is presented. A device is an atomic analogue cell that performs an elementary and standard function such as the differential pair and the current mirror. A device is smart since it can be electrically and physically adapted. In the proposed method, the device sizes and biases are first computed using dedicated sizing operators based on the MOS transistor model and the foundry Design Kit. Once transistor sizes are computed, they are fed to a layout generation tool which offers different layout styles for the same device. The layout is generated with the layout dependent parasitics, including stress effects. These parasitics are then taken into account by the sizing operators. Therefore a loop between sizing and layout generation can be set and executed until the device specifications are met. The method is applied to a differential pair with several layout styles and two distinct technologies.
Complete list of metadata

Cited literature [19 references]  Display  Hide  Download
Contributor : Stephanie Youssef Connect in order to contact the contributor
Submitted on : Thursday, November 8, 2012 - 3:31:30 PM
Last modification on : Friday, January 8, 2021 - 5:32:07 PM
Long-term archiving on: : Saturday, February 9, 2013 - 3:49:05 AM


Files produced by the author(s)



Stéphanie Youssef, Farakh Javid, Damien Dupuis, Ramy Iskander, Marie-Minerve Louërat. A Seamless Representation for Coupling Transistor Sizing with Nanometric CMOS Layout Generation. 20th European Conference on Circuit Theory and Design (ECCTD), Aug 2011, Linkoping, Sweden. pp.341-344, ⟨10.1109/ECCTD.2011.6043356⟩. ⟨hal-00749892⟩



Les métriques sont temporairement indisponibles