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Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations

Abstract : The simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). The SystemC TLM2.0 (Transaction Level Modeling) approach accelerates the simulation by using Interface Method Calls (IMC) to implement the communications between hardware components. Another source of speedup can be exploited by parallel simulation. Multi-core workstations are becoming the mainstream, and SMP workstations will soon contain several tens of cores. The standard SystemC simulation engine uses a centralized scheduler, that is clearly the bottleneck for a parallel simulation. This paper has two main contributions. The first is a general modeling strategy for shared memory MPSoCs, called TLM-DT (Transaction Level Modeling with Distributed Time). The second is a truly parallel simulation engine, called SystemC-SMP. First experimental results on a 40 processor MPSoC virtual prototype running on a dual-core workstation demonstrate a 1.8 speedup, versus a sequential simulation.
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Contributor : Aline Vieira de Mello <>
Submitted on : Sunday, November 4, 2012 - 11:47:04 AM
Last modification on : Thursday, March 21, 2019 - 1:04:00 PM


  • HAL Id : hal-00748083, version 1


Aline Vieira de Mello, Isaac Maia Pessoa, Alain Greiner, François Pêcheux. Parallel Simulation of SystemC TLM 2.0 Compliant MPSoC on SMP Workstations. DATE 2010 - Design, Automation & Test in Europe Conference & Exhibition, Mar 2010, Dresden, Germany. pp.606-609. ⟨hal-00748083⟩



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