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Communication Dans Un Congrès Année : 2012

Enhanced Reduced Code Linearity Test Technique for Multi-bit/Stage Pipeline ADCs

Résumé

The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.

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Dates et versions

hal-00744573 , version 1 (23-10-2012)

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Citer

A. Laraba, Haralampos-G Stratigopoulos, Salvador Mir, H. Naudet, C. Forel. Enhanced Reduced Code Linearity Test Technique for Multi-bit/Stage Pipeline ADCs. IEEE 17th European Test Symposium (ETS'12), May 2012, Annecy, France. pp.1 - 6, ⟨10.1109/ETS.2012.6233009⟩. ⟨hal-00744573⟩

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