Rigorous System Level Modeling and Analysis of Mixed HW/SW Systems

Paraskevas Bourgos (1) , Ananda Basu (1) , Saddek Bensalem (1) , Marius Bozga (1) , Joseph Sifakis (1) , Kai Huang (2)

1 VERIMAG - IMAG - VERIMAG
2 Institute of VLSI Design

A grand challenge in complex embedded systems design is developing methods and tools for modeling and analyzing the behavior of an application software running on multicore or distributed platforms. We propose a rigorous method and a tool chain that allows to obtain a faithful model representing the behavior of a mixed hardware/software system from a model of its application software and a model of its underlying hardware architecture. The system model can be simulated and analyzed for validation of both functional and extra-functional properties. The tool chain uses DOL (Distributed Operation Layer [1]) as the frontend for specifying the application software and hardware architecture, and BIP (Behavior Interaction Priority [2]) as the modeling and analysis framework. It is illustrated through the construction of system models of MJPEG and MPEG2 decoder applications running on MPARM, a multicore architecture.

Domaines: Systèmes embarqués

Paraskevas Bourgos, Ananda Basu, Saddek Bensalem, Marius Bozga, Joseph Sifakis, et al.. Rigorous System Level Modeling and Analysis of Mixed HW/SW Systems. 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, MEMOCODE 2011, Jul 2011, Cambridge, United Kingdom. pp.11-20, ⟨10.1109/MEMCOD.2011.5970506⟩. ⟨hal-00722402⟩