MASH Δ-Σ DPWM based sliding-mode controller dedicating to high frequency SMPS
Résumé
The high resolution digital pulse width modulator (DPWM) becomes a crucial part in digital controller for power converters that requires a fast system clock, especially applied to a high switching frequency SMPS. This paper proposes two solutions, the dithering Multi-stAge-noise-Shaping (MASH) and the 2-2 MASH delta-sigma (Δ-Σ) DPWM, so as to alleviate the inherent idle tone effects. An improved sliding mode controller (SMC) is also introduced here exhibiting better performance than the traditional PID compensator. Mixed-signal simulation are presented to demonstrate the theoretical analysis. Experimental results verify the SMPS close-loop operation on 3 V input with 5 V output, 1 A DC-DC boost converter at 1 MHz switching frequency, using a Virtex-II FPGA platform. A digital controller integrated chip (IC) including both DPWM and SMC is introduced as a verification prototype that potentially achieves switching frequency beyond 10MHz.