Distributed synchronous clocking, IEEE Transactions on Parallel and Distributed Systems, vol.6, issue.3, pp.314-342, 1995. ,
DOI : 10.1109/71.372779
Active GHz clock network using distributed PLLs, IEEE Journal of Solid-State Circuits, vol.35, issue.11, pp.1553-60, 2000. ,
DOI : 10.1109/4.881199
Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI, IEEE Journal of Solid-State Circuits, vol.21, issue.2, pp.240-246, 1986. ,
DOI : 10.1109/JSSC.1986.1052510
A multi-PLL clock distribution architecture for gigascale integration, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, pp.30-35, 2001. ,
DOI : 10.1109/IWV.2001.923136
Sync: The Emerging Science of Spontaneous Order, 2003. ,
Network synchronization, Proceedings of the IEEE, vol.73, issue.10, pp.1445-67, 1985. ,
DOI : 10.1109/PROC.1985.13317
Distributed synchronization in wireless networks, Proc. IEEE, pp.81-97, 2008. ,
DOI : 10.1109/MSP.2008.926661
Synchronized state in networks of digital phase-locked loops, Proceedings of the 8th IEEE International NEWCAS Conference 2010, pp.89-92, 2010. ,
DOI : 10.1109/NEWCAS.2010.5603916
Determination of the behaviour of self-sampled digital phase-locked loops, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, pp.1089-1092, 2010. ,
DOI : 10.1109/MWSCAS.2010.5548840
Limit cycles in Digital Bang-Bang PLLs, 2007 18th European Conference on Circuit Theory and Design, pp.731-734, 2007. ,
DOI : 10.1109/ECCTD.2007.4529700
Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems, Phase-Locking in High-Performance Systems, B. Razavi, pp.34-45, 2003. ,
A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.52, issue.1, pp.21-31, 2005. ,
DOI : 10.1109/TCSI.2004.840089
Time-Domain Modeling of an RF All-Digital PLL, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.55, issue.6, pp.601-605, 2008. ,
DOI : 10.1109/TCSII.2007.916845
Stability analysis of piecewise discrete-time linear systems, IEEE Transactions on Automatic Control, vol.47, issue.7, pp.1108-1120, 2002. ,
DOI : 10.1109/TAC.2002.800666
Computation of piecewise quadratic Lyapunov functions for hybrid systems, IEEE Transactions on Automatic Control, vol.43, issue.4, pp.555-559, 1998. ,
DOI : 10.1109/9.664157
Phaselock Techniques, 1979. ,
DOI : 10.1002/0471732699
Design and VHDL modeling of all-digital PLLs, Proceedings of the 8th IEEE International NEWCAS Conference 2010, pp.293-296, 2010. ,
DOI : 10.1109/NEWCAS.2010.5603947
URL : https://hal.archives-ouvertes.fr/hal-00551825
Some applications of Laplace eigenvalues of graphs, Graph Symmetry: Algebraic Methods and Applications, Kluwer, pp.225-275, 1997. ,
DOI : 10.1007/978-94-015-8937-6_6