Graphical method for the phase noise optimization applied to a 6-GHz fully integrated NMOS differential LC VCO

Dorra Mellouli (1, 2) , David Cordeau (3) , Jean-Marie Paillot (3) , Hasséne Mnif (1) , Mourad Loulou (4)

1 CEM Lab - ENIS - Département de Génie Électrique de Sfax [ENIS]
2 LAII [Poitiers] - Laboratoire d'automatique et d'informatique industrielle [EA 1219]
3 SIC
4 Laboratory of Electronics and Information Technologies

This paper describes the design and the optimization in terms of phase noise of a fully integrated NMOS Voltage Controlled Oscillator (VCO) using a 0.25 μm BICMOS SiGe process. A three-dimensional phase noise analysis diagram and a graphical optimization approach is presented to optimize the phase noise of the VCO while satisfying design constraints such as tank amplitude, power dissipation, tuning range and start up conditions. At 2.5 V power supply voltage, the optimized VCO features a simulated phase noise of -118 dBc/Hz at 1 MHz frequency offset from a 6.12 GHz carrier. The VCO is tuned from 6.1 GHz to 7.9 GHz with a tuning voltage varying from 0 to 2.5 V, and a power dissipation of only 7.4 mW.

Domaines: Electronique

Dorra Mellouli, David Cordeau, Jean-Marie Paillot, Hasséne Mnif, Mourad Loulou. Graphical method for the phase noise optimization applied to a 6-GHz fully integrated NMOS differential LC VCO. IEEE 9th International New Circuits and Systems Conference, Jun 2011, Bordeaux, France. pp.85-88. ⟨hal-00683381⟩