Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design

S. Ghosh (1) , B. Grandchamp (1) , G.A Koné , F. Marc (1) , C. Maneux (1) , T. Zimmer (1) , V. Nodjiadjim (2) , M. Riet (2) , J.-Y. Dupuy , J. Godin (2)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 III-V Lab - Alcatel-Thalès III-V lab

Domaines: Micro et nanotechnologies/Microélectronique

S. Ghosh, B. Grandchamp, G.A Koné, F. Marc, C. Maneux, et al.. Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design. Microelectronics Reliability, 2011, 51 (9-11), pp. 1736-1741. ⟨hal-00671676⟩