Hardware architectures for successive cancellation decoding of polar codes

Camille Leroux (1) , Ido Tal (2) , Alexander Vardy (2) , Warren J. Gross (3)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 UC San Diego - University of California [San Diego]
3 McGill University = Université McGill [Montréal, Canada]

The recently-discovered polar codes are widely seen as a major breakthrough in coding theory. These codes achieve the capacity of many important channels under successive cancellation decoding. Motivated by the rapid progress in the theory of polar codes, we pro pose a family of architectures for efficient hardware implementation of successive cancellation decoders. We show that such decoders can be implemented with O(n) processing elements and O(n) memory elements, while providing constant throughput. We also pro pose a technique for overlapping the decoding of several consecutive codewords, thereby achieving a significant speed-up factor. We furthermore show that successive cancellation decoding can be implemented in the logarithmic domain, thereby eliminating the multiplication and division operations and greatly reducing the complexity of each processing element.

Mots clés: consecutive codeword; hardware architecture; logarithmic domain; polar code; speed-up factor; successive cancellation decoding; block codes; channel coding; computational complexity; error correction codes; linear codes

Domaines: Electronique

Camille Leroux, Ido Tal, Alexander Vardy, Warren J. Gross. Hardware architectures for successive cancellation decoding of polar codes. Acoustics, Speech and Signal Processing (ICASSP), 2011 IEEE International Conference on, May 2011, Prague, France. pp.1665 -1668, ⟨10.1109/ICASSP.2011.5946819⟩. ⟨hal-00670695⟩