Design Challenges of a Fully Integrated 65 nm CMOS Half Cascode SFDS PA

Yohann Luque (1) , Eric Kerherve (1) , Nathalie Deltimple (1) , Didier Belot (2)

1 IMS - Laboratoire de l'intégration, du matériau au système
2 ST-CROLLES - STMicroelectronics [Crolles]

This paper presents a 65nm CMOS-Power Amplifier (PA) designed for mobile communications. The PA is based on a new structure, the Stacked Folded Differential (SFD) which is inspired by a push-pull structure. The PA is designed for the UMTS W-CDMA standard which requires linearity from -20 dBm to 24 dBm output power. The PA provides 27 dBm maximal output power (Pmax) with 15% of power added efficiency (PAE) at 1.8 GHz under 2.2 V supply. The linear gain is 13 dB and the compression point (OCP1) is 25.5 dBm. With a HPSK modulation, the adjacent channel leakage ratio (ACLR) of this PA is respected until 23 dBm with 34.17 dBc and 33.70 dBc at 5MHz and +5MHz respectively. The die area of this 65 nm CMOS PA is 0.65mm².

Domaines: Micro et nanotechnologies/Microélectronique

Yohann Luque, Eric Kerherve, Nathalie Deltimple, Didier Belot. Design Challenges of a Fully Integrated 65 nm CMOS Half Cascode SFDS PA. Analog Integrated Circuits and Signal Processing, 2011, vol. 70 (n°2), pp.181-187. ⟨10.1007/s10470-011-9735-1⟩. ⟨hal-00669898⟩