Design of a Mixed-Signal Cartesian Feedback Loop for a Low Power Zero-IF WCDMA Transmitter

Abstract : in this paper, an improved digital-stage design of a mixed-signal Cartesian Feedback loop for a zero-IF WCDMA transmitter is presented. The new transmitter architecture consists of an analog stage including filters, I/Q modulator, feedback I/Q demodulator and a digital stage which adjusts the phase misalignment around the loop. We propose an optimized CORDIC design for the digital part in order to improve the system operating frequency without increasing the silicon surface area. ASIC synthesis proves that using a not fully pipelined CORDIC architecture allows us to reach 230 MHz with system power consumption under 4.3 mw which is two times less than a fully analog system.
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Submitted on : Tuesday, February 14, 2012 - 10:29:44 AM
Last modification on : Wednesday, September 11, 2019 - 5:46:12 PM
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Walid Sanaa, Nicolas Delaunay, Bertrand Le Gal, Dominique Dallet, Chiheb Rebai, et al.. Design of a Mixed-Signal Cartesian Feedback Loop for a Low Power Zero-IF WCDMA Transmitter. 3rd IEEE Circuits and Systems Society Latin American Symposium on Circuits and Systems (LASCAS2012), Feb 2012, Mexico. pp.4. ⟨hal-00669883⟩

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