Skip to Main content Skip to Navigation
Conference papers

Design of an 8GSps, 65nm CMOS Wideband Flash Analog-to-Digital Converter

Diego Rossoni Mattos 1 S. Gauffre 2 P. Hellmuth 3 Ph. Cais 2 J.L. Pedroza 3 Jean-Baptiste Begueret 1 Alain Baudry 2
L3AB - Laboratoire d'astrodynamique, d'astrophysique et d'aéronomie de bordeaux, OASU - Observatoire aquitain des sciences de l'univers, LAB - Laboratoire d'Astrophysique de Bordeaux [Pessac], Université Sciences et Technologies - Bordeaux 1
Abstract : This paper describes the design of an 8Gsps flash Analog-to-Digital Converter (ADC) for wideband radio astronomy applications. The ADC contains a track-and-hold (TAH) and a 1-to-4 demultiplexer. Our circuit has been fabricated with the 65nm technology from STMicroelectronics. The post-layout simulations show a Figure of Merit (FoM) of 11.36pJ/conv.step and a power consumption of 480mW at Nyquist sampling condition. The ongoing tests will soon verify these predictions
Document type :
Conference papers
Complete list of metadatas
Contributor : Equipe Conception de Circuits <>
Submitted on : Thursday, January 5, 2012 - 10:40:30 AM
Last modification on : Monday, November 23, 2020 - 2:38:11 PM


  • HAL Id : hal-00656796, version 1


Diego Rossoni Mattos, S. Gauffre, P. Hellmuth, Ph. Cais, J.L. Pedroza, et al.. Design of an 8GSps, 65nm CMOS Wideband Flash Analog-to-Digital Converter. ICECS, Dec 2011, BEYROUTH, Lebanon. pp.22-26. ⟨hal-00656796⟩



Record views