Design of an 8GSps, 65nm CMOS Wideband Flash Analog-to-Digital Converter

Diego Rossoni Mattos 1 S. Gauffre 2 P. Hellmuth 3 Ph. Cais 2 J.L. Pedroza 3 Jean-Baptiste Begueret 1 Alain Baudry 2
2 FORMATION STELLAIRE 2011
L3AB - Laboratoire d'astrodynamique, d'astrophysique et d'aéronomie de bordeaux, OASU - Observatoire aquitain des sciences de l'univers, LAB - Laboratoire d'Astrophysique de Bordeaux [Pessac], Université Sciences et Technologies - Bordeaux 1
Abstract : This paper describes the design of an 8Gsps flash Analog-to-Digital Converter (ADC) for wideband radio astronomy applications. The ADC contains a track-and-hold (TAH) and a 1-to-4 demultiplexer. Our circuit has been fabricated with the 65nm technology from STMicroelectronics. The post-layout simulations show a Figure of Merit (FoM) of 11.36pJ/conv.step and a power consumption of 480mW at Nyquist sampling condition. The ongoing tests will soon verify these predictions
Type de document :
Communication dans un congrès
ICECS, Dec 2011, BEYROUTH, Lebanon. pp.22-26, 2011


https://hal.archives-ouvertes.fr/hal-00656796
Contributeur : Equipe Conception de Circuits <>
Soumis le : jeudi 5 janvier 2012 - 10:40:30
Dernière modification le : jeudi 13 novembre 2014 - 13:47:02

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  • HAL Id : hal-00656796, version 1

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Diego Rossoni Mattos, S. Gauffre, P. Hellmuth, Ph. Cais, J.L. Pedroza, et al.. Design of an 8GSps, 65nm CMOS Wideband Flash Analog-to-Digital Converter. ICECS, Dec 2011, BEYROUTH, Lebanon. pp.22-26, 2011. <hal-00656796>

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