R. St, D. A. Amant, D. Jiménez, and . Burger, Low-power, high-performance analog neural branch prediction, MICRO, pp.447-458, 2008.

A. Baniasadi and A. Moshovos, SEPAS, Proceedings of the 2004 international symposium on Low power electronics and design , ISLPED '04, pp.38-43, 2004.
DOI : 10.1145/1013235.1013250

A. N. Eden and T. N. Mudge, The YAGS branch predictor, Proceedings of the 31st Annual International Symposium on Microarchitecture, 1998.

M. Evers, P. Chang, and Y. N. Patt, Using hybrid branch predictors to improve branch prediction accuracy in the presence of context switches, Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996.

H. Gao, Y. Ma, M. Dimitrov, and H. Zhou, Address-branch correlation: A novel locality for long-latency hard-to-predict branches, 2008 IEEE 14th International Symposium on High Performance Computer Architecture, pp.74-85, 2008.
DOI : 10.1109/HPCA.2008.4658629

H. Gao and H. Zhou, Adaptive information processing: An effective way to improve perceptron predictors, Journal of Instruction Level Parallelism, 2005.

Y. Ishii, K. Kuroyanagi, T. Sawada, M. Inaba, and K. Hiraki, Revisiting local history for improving fused two-level branch predictor, Proceedings of the 3rd Championship on Branch Prediction, 2011.

Y. Ishii, Fused two-level branch prediction with ahead calculation, Journal of Instruction Level Parallelism, 2007.

D. Jimenez, Fast path-based neural branch prediction, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), 2003.
DOI : 10.1109/MICRO.2003.1253199

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.10.828

D. Jiménez, Reconsidering complex branch predictors, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., 2003.
DOI : 10.1109/HPCA.2003.1183523

D. Jiménez, Piecewise linear branch prediction, Proceedings of the 32nd Annual International Symposium on Computer Architecture, 2005.

D. Jiménez, S. W. Keckler, and C. Lin, The impact of delay on the design of branch predictors, Proceedings of the 33rd Annual International Symposium on Microarchitecture, 2000.

D. Jiménez and C. Lin, Dynamic branch prediction with perceptrons, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, 2001.
DOI : 10.1109/HPCA.2001.903263

A. Daniel and . Jiménez, Oh-snap: Optimized hybrid scaled neural analog predictor, Proceedings of the 3rd Championship on Branch Prediction, 2011.

G. H. Loh and D. S. Henry, Predicting conditional branches with fusion-based hybrid predictors, Proceedings.International Conference on Parallel Architectures and Compilation Techniques, 2002.
DOI : 10.1109/PACT.2002.1106015

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.86.3207

S. Mcfarling and D. Wrl, Combining branch predictors, 1993.

P. Michaud, A. Seznec, and R. Uhlig, Trading conflict and capacity aliasing in conditional branch predictors, Proceedings of the 24th Annual International Symposium on Computer Architecture (ISCA-97), 1997.

P. Michaud, A PPM-like, tag-based predictor, Journal of Instruction Level Parallelism, 2005.

N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, Cacti 6.0: A tool to model large caches, pp.2009-85, 2009.

S. T. Pan, K. So, and J. T. Rahmeh, Improving the accuracy of dynamic branch prediction using branch correlation, Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems, 1992.

A. Seznec, Analysis of the O-GEHL branch predictor, Proceedings of the 32nd Annual International Symposium on Computer Architecture, 2005.

A. Seznec, S. Felix, V. Krishnan, and Y. Sazeidès, Design tradeoffs for the ev8 branch predictor, Proceedings of the 29th Annual International Symposium on Computer Architecture, 2002.

A. Seznec, The L-TAGE branch predictor, Journal of Instruction Level Parallelism, 2007.

A. Seznec, A 64 kbytes ISL-TAGE branch predictor, Proceedings of the 3rd Championship Branch Prediction, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00639040

A. Seznec, Storage free confidence estimation for the TAGE branch predictor, 2011 IEEE 17th International Symposium on High Performance Computer Architecture, 2011.
DOI : 10.1109/HPCA.2011.5749750

URL : https://hal.archives-ouvertes.fr/inria-00512130

A. Seznec and P. Michaud, A case for (partially)-tagged geometric history length predictors, Journal of Instruction Level Parallelism, 2006.

E. Sprangle, R. S. Chappell, M. Alsup, and Y. N. Patt, The agree predictor: A mechanism for reducing negative branch history interference, 24 th Annual International Symposium on Computer Architecture, 1995.

T. Yeh and Y. N. Patt, Two-level adaptive training branch prediction, Proceedings of the 24th annual international symposium on Microarchitecture , MICRO 24, 1991.
DOI : 10.1145/123465.123475