A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding

Purushotham Murugappa Velayuthan (1, 2) , Rachid Al Khayat (1, 2) , Amer Baghdadi (1, 2) , Michel Jezequel (1, 2)

1 Lab-STICC_TB_CACS_IAS
2 ELEC - Département Electronique

In order to address the large variety of channel coding options specified in existing and future digital communication standards, there is an increasing need for flexible solutions. This paper presents a multi-core architecture which supports convolutional codes, binary/duo-binary turbo codes, and LDPC codes. The proposed architecture is based on Application Specific Instruction-set Processors (ASIP) and avoids the use of dedicated interleave/deinterleave address lookup memories. Each ASIP consists of two datapaths one optimized for turbo and the other for LDPC mode, while efficiently sharing memories and communication resources. The logic synthesis results yields an overall area of 2.6mm2 using 90nm technology. Payload throughputs of up to 312Mbps in LDPC mode and of 173Mbps in Turbo mode are possible at 520MHz, fairing better than existing solutions.

Mots clés: Turbo decoding; LDPC; Flexible architecture; Flexible receiver; ASIP; Multiprocessor; High Throughput; NoC

Domaines: Micro et nanotechnologies/Microélectronique; Traitement du signal et de l'image [eess.SP]

Purushotham Murugappa Velayuthan, Rachid Al Khayat, Amer Baghdadi, Michel Jezequel. A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. DATE'11: IEEE/ACM Design, Automation and Test in Europe Conference & Exhibition, Mar 2011, Grenoble, France. ⟨hal-00632764⟩