A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΣΔ ADC with a FoM of 1pJ/bit in 130nm CMOS

Ahmed Ashry 1 Hassan Aboushady 1
1 CIAN - Circuits Intégrés Numériques et Analogiques
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : A 4th order RF LC ΔΣ ADC clocked at 3.6GHz and centered at 900MHz is presented. The simplicity of the ADC architecture results in a significant performance enhancement and power consumption reduction. The ADC, suitable for Software Defined Radio applications, is implemented in a standard 130nm CMOS technology. It achieves a 52dB SFDR and a 50dB SNDR in a 28MHz BW and consumes only 15mW from a 1.2V supply. The Figure of Merit of the ADC is 1.0pJ/bit, which is to date the best reported FoM for an RF ADC. An efficient algorithm for the tuning and calibration of the ΔΣ LC-based loop filter is also presented in this paper.
Document type :
Conference papers
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-00626877
Contributor : Ahmed Ashry <>
Submitted on : Tuesday, September 27, 2011 - 11:51:13 AM
Last modification on : Thursday, March 21, 2019 - 1:12:42 PM

Identifiers

Citation

Ahmed Ashry, Hassan Aboushady. A 3.6GS/s, 15mW, 50dB SNDR, 28MHz bandwidth RF ΣΔ ADC with a FoM of 1pJ/bit in 130nm CMOS. CICC 2011 - Custom Integrated Circuits Conference, Sep 2011, San Jose, CA, United States. pp.1-4, ⟨10.1109/CICC.2011.6055292⟩. ⟨hal-00626877⟩

Share

Metrics

Record views

115