A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders

Ali Al Ghouwayel (1) , Emmanuel Boutillon (1)

1 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)

Non-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is the use of the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n_m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols.

Mots clés: NB-LDPC; systolic; LLR generation

Domaines: Electronique

Ali Al Ghouwayel, Emmanuel Boutillon. A Systolic LLR Generation Architecture For Non-Binary LDPC Decoders. IEEE Communications Letters, 2011, 15 (8), pp 851-853. ⟨hal-00608287⟩