M. Pecht and S. Tiku, Bogus ! Electronic manufacturing and consumers confront a rising tide of counterfeit electronics, IEEE Spectrum

D. Gajski, High-Level Synthesis: Introduction to Chip and System Design, 1992.
DOI : 10.1007/978-1-4615-3636-9

R. Chapman and T. Durrani, IP protection of DSP algorithms for system on chip implementation, IEEE Transactions on Signal Processing, vol.48, issue.3, pp.854-861, 2000.
DOI : 10.1109/78.824679

J. Rashid, W. Asher, M. Mangione-smith, and . Potkonjak, Hierarchical watermarking for protection of DSP filter cores, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327), pp.39-42, 1999.
DOI : 10.1109/CICC.1999.777240

E. Torunoglu and . Charbon, Watermarking-based copyright protection of sequential functions, IEEE Journal of Solid-State Circuits, vol.35, issue.3, pp.434-440, 2000.
DOI : 10.1109/4.826826

. Oliveira, Techniques for the creation of digital watermarks in sequential circuit designs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.20, issue.9, pp.1101-1117, 2001.
DOI : 10.1109/43.945306

F. Koushanfar, I. Hong, and M. Potkonjak, Behavioral synthesis techniques for intellectual property protection, ACM Transactions on Design Automation of Electronic Systems, vol.10, issue.3, pp.523-545, 2005.
DOI : 10.1145/1080334.1080338
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.422.3501

D. Kirovski, Y. Y. Hwang, M. Potkonjak, and J. Cong, Intellectual property protection by watermarking combinational logic synthesis solutions, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design , ICCAD '98, pp.194-198, 1998.
DOI : 10.1145/288548.288609
URL : http://andante.eecs.umich.edu/ecad/conferences/papers/1998/iccad98/htmfiles/sun_sgi/././pdffiles/03b_3.pdf

W. H. Lach, M. Mangione-smith, and . Potkonjak, Robust FPGA intellectual property protection through multiple small watermarks, Proceedings of DAC '99, pp.831-836, 1999.
DOI : 10.1109/dac.1999.782152
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.16.1399

A. Cui, C. H. Chang, and S. Tahar, IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, issue.9, pp.1565-1570, 2008.
DOI : 10.1109/TCAD.2008.927732

C. H. Chang and A. Cui, Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.57, issue.7, pp.1618-1630, 2010.
DOI : 10.1109/TCSI.2009.2035415

A. Jain, L. Yuan, P. Pari, and G. Qu, Zero overhead watermarking technique for FPGA designs, Proceedings of the 13th ACM Great Lakes Symposium on VLSI , GLSVLSI '03, pp.147-152, 2003.
DOI : 10.1145/764808.764847

G. Sun, Z. Gao, and Y. Xu, A watermarking system for ip protection by buffer insertion technique, Proc. of ISQED, pp.671-675, 2006.

Y. C. Fan and H. W. Tsao, Watermarking for intellectual property protection, Electronics Letters, vol.39, issue.18, pp.1316-1318, 2003.
DOI : 10.1049/el:20030874

B. , L. Gal, E. Casseau, and S. Huet, Dynamic memory access management for high-performance DSP applications using high-level synthesis, IEEE Transactions on VLSI Systems, vol.16, issue.11, pp.454-1464, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00361870

R. S. Arvind, D. L. Nikhil, N. Rosenband, and . Dave, High-level synthesis: an essential ingredient for designing complex ASICs, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004., pp.775-782, 2004.
DOI : 10.1109/ICCAD.2004.1382681
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.89.8560

P. Coussy, GAUT: A High-Level Synthesis Tool for DSP Applications, High-Level Synthesis from Algorithm to Digital Circuit (XVI), pp.147-169, 2008.
DOI : 10.1007/978-1-4020-8588-8_9
URL : https://hal.archives-ouvertes.fr/hal-00489794