Reliability approach of high density Through Silicon Via (TSV)

T. Frank (1, 2) , C. Chappaz (1) , P. Leduc (3) , L. Arnaud (4) , S. Moreau (5) , Aurélie Thuaire (6) , R. El Farhane (4) , Lorena Anghel (2)

1 ST-CROLLES - STMicroelectronics [Crolles]
2 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
3 IBCP - Institut de biologie et chimie des protéines [Lyon]
4 LGGE - Laboratoire de glaciologie et géophysique de l'environnement
5 IRBI - Institut de recherche sur la biologie de l'insecte
6 SIMaP - Science et Ingénierie des Matériaux et Procédés

This paper focuses on the link between initial electrical resistance of Through Silicon Via (TSV), and possible failure occurring during Thermal Cycling Test (TCT) and electromigration (EM) tests. Physical analyses reveal the presence of a carbon impurity layer at bottom of the higher resistance TSVs. This impurity induces failure during TCT, but has no impact on EM time to failure distribution. We also discuss the relevance of different electrical resistance failure criterions after TCT for a single TSV.

Mots clés: high-density-ASIC

Domaines: Micro et nanotechnologies/Microélectronique

T. Frank, C. Chappaz, P. Leduc, L. Arnaud, S. Moreau, et al.. Reliability approach of high density Through Silicon Via (TSV). 12th Electronics Packaging Technology Conference (EPTC'10), Dec 2010, Singapore, Singapore. pp.321 - 324, ⟨10.1109/EPTC.2010.5702655⟩. ⟨hal-00599560⟩