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Multiple Threshold Voltage for Glitch Power Reduction

Abstract : We address the problem of circuit-level design for low power. We describe a new method for glitch power reduction based on threshold voltage adjustment. The proposed method achieves both dynamic and leakage power reductions. We develop an optimization algorithm that transforms the circuit netlist in an optimized one achieving glitch energy reductions without affecting the overall circuit delay requirement. Applying the algorithm to C17 benchmark circuit implemented in a 65 nm industrial Low Power CMOS process, we have achieved 14% of total energy savings and 78% of leakage energy savings at the expense of just 5% of delay increase.
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Contributor : Philippe Matherat <>
Submitted on : Tuesday, June 7, 2011 - 6:13:58 PM
Last modification on : Friday, July 31, 2020 - 10:44:07 AM
Long-term archiving on: : Friday, September 9, 2011 - 3:21:42 PM


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Mariem Slimani, Philippe Matherat. Multiple Threshold Voltage for Glitch Power Reduction. Faible Tension Faible Consommation (FTFC), 2011, May 2011, Marrakech, Morocco. pp.67-70, ⟨10.1109/FTFC.2011.5948921⟩. ⟨hal-00598877⟩



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