Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case

O. Elissati (1) , E. Yahya (1, 2) , S. Rieubon (3) , Laurent Fesquet (1)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 Higher Institute of Technology, Banha University
3 ST-Ericsson [Grenoble]

Self-timed rings are a promising approach for designing high-speed serial links or clock generators. This study focuses on the ring stage components – a C-element and an inverter - and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage - only composed by a C-element with complementary outputs - which allows us to increase the maximum speed of 25% and reduce the power consumption of 60% at the maximum frequency. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics.

Mots clés: self-timed-rings; CMOS

Domaines: Micro et nanotechnologies/Microélectronique

O. Elissati, E. Yahya, S. Rieubon, Laurent Fesquet. Optimizing and Comparing CMOS Implementations of the C-element in 65nm technology: Self-Timed Ring Case. International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2010), Sep 2010, Grenoble, France. ⟨hal-00569495⟩