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Design simulation of decimation filter for sigma delta converters

Abstract : The purpose of this paper is to present several filter topologies used for decimation of sigma delta modulated digital signals in order to choose the optimised filter architecture with regards to an efficient implementation. The filter is suited for data conversion and measurement applications. A second order 1-bit sigma delta modulator will be considered as the front-end A/D converter. The subsequent digital filter reduces the sampling rate by a factor of 64 and must guarantee a stop band attenuation of 80 dB
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Contributor : Dominique Dallet <>
Submitted on : Tuesday, February 22, 2011 - 11:53:51 AM
Last modification on : Thursday, January 11, 2018 - 6:21:08 AM


  • HAL Id : hal-00567951, version 1


Sonia Boujelben, Chiheb Rebai, Dominique Dallet, Philippe Marchegay. Design simulation of decimation filter for sigma delta converters. IWADC 2001, Sep 2001, Lisbone, Portugal. pp.111-115. ⟨hal-00567951⟩



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