A codesign synthesis from an MPEG-4 decoder dataflow description
Résumé
The elaboration of new and innovative systems such as MPSoC (Multiprocessor System on Chip) which are made up of multiple processors, memories and IPs lies on the designers to achieve a complex codesign work. Specific tools and methods are needed to cope with the increasing complexity of both algorithms and platforms. Our approach to design such systems is based on the usage of a high level of abstraction language called RVC CAL. This language is dataflow oriented and thus points out the concurrency and parallelism of algorithms. Moreover CAL is supported by the OpenDF simulator and by two code generators called CAL2C (software generator) and CAL2HDL (hardware generator). The MPEG expert group has recently elaborated the Reconfigurable Video Coding (RVC) standard which defines the RVC CAL language as reference for MPEG video decoder descriptions. This paper introduces the opportunities to design an innovative system involving hardware and software IPs, embedded processors and memories from a CAL model. Practical results on a FPGA are provided with a codesign solution of an MPEG4 Simple Profile (SP).
Mots clés
CAL model
IP
MPEG-4
MPSoC
RVC
abstraction language
codesign synthesis
decoder dataflow
embedded processor
innovative system
multiple processor
multiprocessor system on chip
reconfigurable video coding
data flow computing
hardware description languages
hardware-software codesign
multiprocessing systems
parallel memories
reconfigurable architectures
system-on-chip
video coding
Domaines
Systèmes embarqués
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