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Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

Abstract : Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word- length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC.
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https://hal.archives-ouvertes.fr/hal-00554228
Contributor : Bertrand Le Gal <>
Submitted on : Monday, January 10, 2011 - 3:02:05 PM
Last modification on : Monday, May 11, 2020 - 1:56:03 PM

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Bertrand Le Gal, Emmanuel Casseau. Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis. Journal of Signal Processing Systems, Springer, 2011, 2011 (63(1)), pp.341-357. ⟨10.1007/s11265-010-0467-8⟩. ⟨hal-00554228⟩

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