Low-cost hardware implementations for discrete-time spiking neural networks

Horacio Rostro-Gonzalez (1) , Jose Hugo Barron-Zambrano (2) , Cesar Torres-Huitzil (3) , Bernard Girau (3)

1 NEUROMATHCOMP - Neurosciences Mathématique et Computationnelle
2 Laboratorio de Tecnologías de Información de Cinvestav Tamaulipas
3 CORTEX - Neuromimetic intelligence

In this paper, both GPU (Graphing Processing Unit) based and FPGA (Field Programmable Gate Array) based hardware implementations for a discrete-time spiking neuron model are presented. This generalized model is highly adapted for large scale neural network implementations, since its dynamics are entirely represented by a spike train (binary code). This means that at microscopic scale the membrane potentials have a one-to-one correspondence with the spike train, in the asymptotic dynamics. This model also permit us to reproduce complex spiking dynamics such as those obtained with general Integrate-and-Fire (gIF) models. The FPGA design has been coded in Handel-C and VHDL and has been based on a fixed-point reconfigurable architecture, while the GPU spiking neuron kernel has been coded using C++ and CUDA. Numerical verifications are provided.

Mots clés: Neuron models; Others

Domaines: Neurosciences [q-bio.NC]; Neurosciences

Horacio Rostro-Gonzalez, Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Bernard Girau. Low-cost hardware implementations for discrete-time spiking neural networks. Cinquième conférence plénière française de Neurosciences Computationnelles, "Neurocomp'10", Aug 2010, Lyon, France. ⟨hal-00553431⟩