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Article Dans Une Revue Materials Science Forum Année : 2010

Minimization of drain-to-gate interaction in a SiC JFET inverter using an external gate-source capacitor

Youness Hamieh
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Dominique Bergogne
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Hervé Morel

Résumé

This paper presents a study on a SiC JFET leg of a 3-leg Voltage Source Inverter (VSI). The switching curves obtained with the JFET working in free wheeling mode are shown to point out drain-to-gate interaction effects. Indeed, during the drain-source voltage variations, the JFET gate-source voltage can have considerable variations, because of the electrical coupling induced by the gate-drain capacitance Cgd. When the gate-source voltage variation becomes too negative, there is a risk of occurrence of the phenomenon of punch-through in the gate-source junction. Conversely, when it is enough positive, the JFET may conduct and lead to a leg short-circuit. To decrease these undesired effects for the JFET legs and consequently for the SiC JFET inverter, an external gate-source capacitor is used. This solution is studied and optimized by simulation on an inverter leg. © (2010) Trans Tech Publications, Switzerland.
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Dates et versions

hal-00539615 , version 1 (24-11-2010)

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Olivier Berry, Youness Hamieh, Stéphane Rael, Farid Meibody-Tabar, Sébastien Vieillard, et al.. Minimization of drain-to-gate interaction in a SiC JFET inverter using an external gate-source capacitor. Materials Science Forum, 2010, 645-6648, pp.957-960. ⟨10.4028/www.scientific.net/MSF.645-64⟩. ⟨hal-00539615⟩
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