Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9 4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi Standard Local Oscillator

Abstract : This paper presents the design and the measurement results of a novel Voltage Controlled Delay Line (VCDL) dedicated to an original architecture of Delay Locked Loop (DLL): the Factorial Delay Locked Loop (F-DLL). Based on the multiphase ring oscillator technique, the proposed VCDL offers, among others, two outputs in phase quadrature. These last ones allow the F-DLL to be zero-IF compliant and becomes a good candidate for multi-standard local oscillator. The proposed circuit has been fabricated in a 130nm CMOS-SOI technology from STMicroelectronics. Measurement results confirm the low quadrature phase error of the topology (inferior to 5°) and the ability of the F-DLL to synthesize the [0.9-4] GHz band, being suited for GSM up to WIMAX applications, while offering very interesting performances in term of phase noise and settling time
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https://hal.archives-ouvertes.fr/hal-00539233
Contributor : Equipe Conception de Circuits <>
Submitted on : Wednesday, November 24, 2010 - 2:32:13 PM
Last modification on : Wednesday, October 9, 2019 - 9:30:27 PM

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  • HAL Id : hal-00539233, version 1

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Cédric Majek, Pierre-Olivier Lucas de Peslouan, André Mariano, Herve Lapuyade, Yann Deval, et al.. Voltage Controlled Delay Line with Phase Quadrature Outputs for [0.9 4]GHz Factorial Delay Locked Loop Dedicated to Zero-IF Multi Standard Local Oscillator. Journal of Integrated Circuits and Systems, Brazilian Microelectronics Society, 2010, pp.150-165. ⟨hal-00539233⟩

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