E. [. Adams, D. Balas, and . Zawack, The Shifting Bottleneck Procedure for Job Shop Scheduling, Management Science, vol.34, issue.3, pp.391-401, 1988.
DOI : 10.1287/mnsc.34.3.391

L. [. Balasubramanian, J. W. Mönch, M. E. Fowler, and . Pfund, Genetic algorithm based scheduling of parallel batch machines with incompatible job families to minimize total weighted tardiness, International Journal of Production Research, vol.1, issue.8, pp.1621-1638, 2004.
DOI : 10.1016/S0305-0548(01)00031-4

R. Cigolini, M. Perona, A. Portioli, and T. Zambelli, A new dynamic look-ahead scheduling procedure for batching machines, Journal of Scheduling, vol.5, issue.2, pp.185-204, 2002.
DOI : 10.1002/jos.99

R. [. Demirkol and . Uzsoy, Decomposition methods for reentrant flow shops with sequence-dependent setup times, Journal of Scheduling, vol.38, issue.3, pp.155-177, 2000.
DOI : 10.1002/(SICI)1099-1425(200005/06)3:3<155::AID-JOS39>3.0.CO;2-E

K. [. Gentner, C. Neumann, N. Schwindt, and . Trautmann, Batch production scheduling in the process industries Handbook of Scheduling: Algorithms, Models and Performance Analysis, pp.48-49, 2004.

C. Glassey and M. Resende, Closed-loop job release control for VLSI circuit manufacturing, IEEE Transactions on Semiconductor Manufacturing, vol.1, issue.1, pp.36-46, 1988.
DOI : 10.1109/66.4371

. Icn-+-03-]-k, M. A. Ibrahim, W. S. Chik, N. L. Nizam, and N. F. Fem, Za'bah. Efficient lot batching system for furnace operation, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp.322-324, 2003.

C. [. Kirkpatrick, M. Gelatt, and . Vecchi, Optimization by Simulated Annealing, Science, vol.220, issue.4598, pp.671-680, 1983.
DOI : 10.1126/science.220.4598.671

[. Kim, B. Joo, and S. Choi, Scheduling wafer lots on diffusion machines in a semiconductor wafer fabrication facility, IEEE Transactions on Semiconductor Manufacturing, vol.23, issue.2, pp.246-254, 2010.

]. P. Kum94 and . Kumar, Scheduling semiconductor manufacturing plants, IEEE Control Systems Magazine, vol.14, issue.6, pp.30-40, 1994.

]. J. Lit61 and . Little, A proof for the queuing formula l = ?w, Operations Research, vol.16, pp.651-665, 1961.

L. Mönch, H. Balasubramanian, J. W. Fowler, and M. E. Pfund, Heuristic scheduling of jobs on parallel batch machines with incompatible job families and unequal ready times, Computers & Operations Research, vol.32, issue.11, pp.2731-2750, 2005.
DOI : 10.1016/j.cor.2004.04.001

J. [. Mason, W. M. Fowler, and . Carlyle, A modified shifting bottleneck heuristic for minimizing total weighted tardiness in complex job shops, Journal of Scheduling, vol.100, issue.3, pp.247-262, 2002.
DOI : 10.1002/jos.102

. Mfdp-+-09-]-l, J. W. Mönch, S. Fowler, S. Dauzère-pérès, O. Mason et al., Scheduling semiconductor manufacturing operations: Problems, solution techniques, and future challenges, 4th Multidisciplinary International Conference on Scheduling: Theory & Applications, 2009.

L. Mönch and I. Habenicht, Simulation-based assessment of batching heuristics in semiconductor manufacturing, Proceedings of the 2003 International Conference on Machine Learning and Cybernetics (IEEE Cat. No.03EX693), pp.1338-1345, 2003.
DOI : 10.1109/WSC.2003.1261570

K. [. Mason and . Oey, Scheduling complex job shops using disjunctive graphs: a cycle elimination procedure Mathirajan and A. I. Sivakumar. A literature review, classification and simple metaanalysis on scheduling of batch processors in semiconductor manufacturing, International Journal of Production Research International Journal of Advanced Manufacturing Technology, vol.5, issue.29, pp.981-994990, 2003.

]. M. Ms06b, A. I. Mathirajan, and . Sivakumar, Minimizing total weighted tardiness on heterogeneous batch processing machines with incompatible job families, International Journal of Advanced Manufacturing Technology, vol.28, pp.1038-1047, 2006.

[. Mehta and R. Uzsoy, Manufacturing performance evaluation in wafer semiconductor factories Minimizing total tardiness on a batch processing machine with incompatible job families, International Journal of Productivity and Performance management IIE Transactions, vol.554, issue.30, pp.300-310165, 1998.

G. [. Oulamara, A. Finke, and . Kamgain-kuiten, Flowshop scheduling problem with a batching machine and task compatibilities, Computers & Operations Research, vol.36, issue.2, pp.391-401, 2009.
DOI : 10.1016/j.cor.2007.10.006
URL : https://hal.archives-ouvertes.fr/hal-00185479

S. [. Oey and . Mason, Scheduling batch processing machines in complex job shops, Proceeding of the 2001 Winter Simulation Conference (Cat. No.01CH37304), pp.1200-1207, 2001.
DOI : 10.1109/WSC.2001.977434

R. [. Ovacik and . Uzsoy, Decomposition methods for complex factory scheduling problems, 1997.
DOI : 10.1007/978-1-4615-6329-7

. E. Pbf-+-08-]-m, H. Pfund, J. W. Balasubramanian, S. J. Fowler, O. Mason et al., A multi-criteria approach for scheduling semiconductor wafer fabrication facilities, Journal of Scheduling, vol.11, issue.1, pp.29-47, 2008.

J. [. Perez, W. M. Fowler, and . Carlyle, Minimizing total weighted tardiness on a single batch process machine with incompatible job families, Computers & Operations Research, vol.32, issue.2, pp.327-341, 2005.
DOI : 10.1016/S0305-0548(03)00239-9

Y. [. Sung and . Kim, Minimizing due date related performance measures on two batch processing machines, European Journal of Operational Research, vol.147, issue.3, pp.644-65695, 2001.
DOI : 10.1016/S0377-2217(02)00352-1

]. Su03 and . Su, A hybrid two-stage flow shop with limited waiting time constraints, Computers and Industrial Engineering, vol.44, pp.409-424, 2003.

]. S. Sze01 and . Sze, Semiconductor devices: Physics and technology, 2001.

C. [. Uzsoy and . Wang, Performance of decomposition procedures for job shop scheduling problems with bottleneck machines, International Journal of Production Research, vol.38, issue.6, pp.1271-1286, 2000.
DOI : 10.1080/002075400188843

]. R. Uzs95 and . Uzsoy, Scheduling batch processing machines with incompatible job families, International Journal of Production research, vol.33, pp.2685-2708, 1995.

A. Varadarajan and S. C. Sarin, A SURVEY OF DISPATCHING RULES FOR OPERATIONAL CONTROL IN WAFER FABRICATION, 12th IFAC Symposium on Information Control Problems in Manufacturing, pp.715-726, 2006.
DOI : 10.3182/20060517-3-FR-2903.00363

]. L. Wei88 and . Wein, Scheduling semiconductor wafer fabrication, IEEE Transactions on Semiconductor Manufacturing, vol.1, issue.3, pp.115-130, 1988.