Electrical properties of polysilicon nanowires for devices applications
Résumé
In this work, we processed polysilicon nanowires using the well known and low cost technique commonly used in microelectronic industry: the sidewall spacer formation technique. In our process, a polysilicon layer is deposited by LPCVD (Low Pressure Chemical Vapour Deposition) technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. N-type in-situ doping process of such polysilicon nanowires is ensured by incorporation of phosphine during deposition of polysilicon. Polysilicon nanowires were integrated into the fabrication of electrical devices as resistors. Effect of in situ phosphorus doping was investigated, doping levels varying from 1016 to 2.1020 at/cm3. Polysilicon nanowires dark conductivity versus temperature was measured leading to the determination of conductivity activation energy values that are compared to those obtained for corresponding polysilicon layers. In addition, Thin Film Transistors were also fabricated using polysilicon nanowires as channel region highlighting a very promising field effect behaviour.