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A FPGA-prototype of a sliding-mode-controller IC for high-switching-frequency DC-DC converters

Abstract : A sliding mode control (SMC) algorithm dedicated to switching mode power supply (SMPS) is validated experimentally in a FPGA. A constant high switching frequency is obtained using an hybrid digital pulse width modulator (DPWM). The proposed SMC strategy cooperates with an off-chip ADC and the hybrid DPWM takes advantage of a digital clock manager (DCM) and a counter-comparator based DPWM with a Multi-stAage-noise-SHaping (MASH) ¿-¿ modulator. Experimental results verify closed-loop operation at switching frequency up to 4 MHz only limited by the discrete SMPS and its dynamic response less than 30 ¿s. Simulation results show that the complete digital controller chip in 0.35 ¿m CMOS process takes 0.72 mm2 of silicon area and the current consumption is roughly 100 ¿A/MHz for a dynamic response of 16 ¿s.
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https://hal.archives-ouvertes.fr/hal-00476274
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Submitted on : Sunday, April 25, 2010 - 11:31:47 PM
Last modification on : Tuesday, April 7, 2020 - 2:01:09 AM

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Shuibao Guo, Xuefang Lin-Shi, Bruno Allard, Bo Li, Yanxia Gao, et al.. A FPGA-prototype of a sliding-mode-controller IC for high-switching-frequency DC-DC converters. 35th IEEE IECON, Nov 2009, Porto, Portugal. pp.2895 - 2900, ⟨10.1109/IECON.2009.5415268⟩. ⟨hal-00476274⟩

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