B. Bhattacharya and S. S. Bhattacharyya, Parameterized dataflow modeling for DSP systems, IEEE Transactions on Signal Processing, vol.49, issue.10, pp.2408-2421, 2001.
DOI : 10.1109/78.950795

M. R. Garey and D. S. Johnson, Computers and Intractability ; A Guide to the Theory of NP-Completeness, 1990.

T. Grandpierre and Y. Sorel, From algorithm and architecture specification to automatic generation of distributed realtime executives: a seamless flow of graphs transformations, International Conference on Formal Methods and Models for Codesign, MEMOCODE'03, 2003.

C. Hsu, J. L. Pino, and S. S. Bhattacharyya, Multithreaded simulation for synchronous dataflow graphs, Proceedings of the Design Automation Conference, pp.331-336, 2008.
DOI : 10.1145/1391469.1391553
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.143.3529

E. Lee and D. Messerschmitt, Pipeline interleaved programmable DSP's: Synchronous data flow programming, Proceedings of the IEEE, pp.1334-1345, 1987.
DOI : 10.1109/TASSP.1987.1165275

E. A. Lee and D. G. Messerschmitt, Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing, IEEE Transactions on Computers, vol.36, issue.1, pp.24-35, 1987.
DOI : 10.1109/TC.1987.5009446

M. Pelcat, P. Menuet, S. Aridhi, and J. Nezan, Scalable compile-time scheduler for multi-core architectures, 2009 Design, Automation & Test in Europe Conference & Exhibition, 2009.
DOI : 10.1109/DATE.2009.5090909
URL : https://hal.archives-ouvertes.fr/hal-00429393

J. Piat, S. S. Bhattacharyya, and M. Raulet, Interface-based hierarchy for synchronous data-flow graphs, 2009 IEEE Workshop on Signal Processing Systems, 2009.
DOI : 10.1109/SIPS.2009.5336240
URL : https://hal.archives-ouvertes.fr/hal-00440478

J. Piat, M. Raulet, M. Pelcat, P. Mu, and O. Déforges, An extensible framework for fast prototyping of multiprocessor dataflow applications, 2008 3rd International Design and Test Workshop, 2008.
DOI : 10.1109/IDT.2008.4802500
URL : https://hal.archives-ouvertes.fr/hal-00398830

J. L. Pino, S. S. Bhattacharyya, and E. A. Lee, A hierarchical multiprocessor scheduling system for DSP applications, Conference Record of The Twenty-Ninth Asilomar Conference on Signals, Systems and Computers, pp.122-126, 1995.
DOI : 10.1109/ACSSC.1995.540525

H. W. Printz, <title>Automatic Mapping Of Large Signal Processing Systems To A Parallel Machine</title>, Real-Time Signal Processing XII, 1991.
DOI : 10.1117/12.962367

G. C. Sih and E. A. Lee, Dynamic-level scheduling for heterogeneous processor networks, Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing 1990, pp.42-49, 1990.
DOI : 10.1109/SPDP.1990.143505

O. Sinnen and L. Sousa, Communication contention in task scheduling, IEEE Transactions on Parallel and Distributed Systems, vol.16, issue.6, pp.503-515, 2005.
DOI : 10.1109/TPDS.2005.64
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.322.523

W. Sung, M. Oh, C. Im, and S. Ha, Demonstration Of Codesign Workflow In PeaCE, Proc. of International Conference of VLSI Circuit, 1997.