Scalable Compile-Time Scheduler for Multi-core Architectures

Abstract : As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing interest. This scheduling consists of statically distributing the tasks that constitute an application between available cores in a multi-core architecture in order to minimize the final latency. This problem has been proven to be NP-complete. A static scheduling algorithm is usually described as a monolithic process, and carries out two distinct functionalities: choosing the core to execute a specific function and evaluating the cost of the generated solutions. This paper describes a scheduling module which splits these functionalities into two sub-modules. This division produces an advanced scalability in terms of schedule quality and computation time, and also separates the heuristic complexity from the architecture model precision.
Type de document :
Communication dans un congrès
Design, Automation and Test in Europe, DATE 2009, Apr 2009, Nice, France. IEEE, pp. 1552-1555, 2009
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https://hal.archives-ouvertes.fr/hal-00429393
Contributeur : Jean François Nezan <>
Soumis le : lundi 2 novembre 2009 - 16:41:22
Dernière modification le : mardi 5 février 2019 - 15:58:19

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  • HAL Id : hal-00429393, version 1

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Maxime Pelcat, Pierrick Menuet, Jean François Nezan, Slaheddine Aridhi. Scalable Compile-Time Scheduler for Multi-core Architectures. Design, Automation and Test in Europe, DATE 2009, Apr 2009, Nice, France. IEEE, pp. 1552-1555, 2009. 〈hal-00429393〉

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