Rapid prototyping of ASIP-based flexible MMSE-IC linear equalizer

Atif Raza Jafri (1, 2) , Amer Baghdadi (3) , Michel Jezequel (3)

1 ELEC - Département Electronique
2 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
3 Lab-STICC_TB_CACS_IAS

Rapid emergence of diverse wireless communication standards implies two crucial requirements on hardware implementation: (1) Hardware platform flexibility for multistandard support, and (2) Rapid prototyping methodology for system validation under different use case scenarios. ASIP based platform, designed through Architecture Description Language(ADL) fulfills both of these requirements in an elegant way. This paper presents the design summary and prototyping flow of an ASIP-based flexible MMSE-IC Linear Equalizer for MIMO Turbo-Equalization Applications. The rapid development and prototyping flow has been described starting from LISA ADL description till the FPGA implementation. Using a logic emulation board integrating Virtex 5 FPGA,the prototype of 2×2 spatially multiplexed MIMO system achieves a throughput of 65 MSymbol/Sec at a clock frequency of 130MHz.

Mots clés: Turbo equalization; ASIP; MMSE equalizer; FPGA prototyping; MIMO systems

Atif Raza Jafri, Amer Baghdadi, Michel Jezequel. Rapid prototyping of ASIP-based flexible MMSE-IC linear equalizer. RSP’09 : IEEE International Symposium on Rapid System Prototyping, Jun 2009, Paris, France. pp.130-133, ⟨10.1109/RSP.2009.17⟩. ⟨hal-00424960⟩