Shared resources high-level modeling in embedded systems using virtual nodes

Chafic Jaber (1, 2, 3, 4, 5) , Andreas Kanstein (2) , Ludovic Apvrille (4, 5) , Amer Baghdadi (6) , Renaud Pacalet (4, 5)

1 ELEC - Département Electronique
2 Freescale - Freescale Semiconductor
3 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)
4 Télécom ParisTech
5 COMELEC - Département Communications & Electronique
6 Lab-STICC_TB_CACS_IAS

The increasing complexity of system-on-chip design and shorter time to market constraints has stimulated systems designers to investigate performance characteristics of the final system implementation in the early design stages, by means of modeling the design at a high level of abstraction. This paper presents the virtual node concept for modeling the shared resources of a system-on-chip, therefore specifically dedicated to the study of the impact of shared resources contention on the overall system’s performance, which is often defined by concurrent use cases. The overall approach is based on using a specific UML modeling profile and a SystemC-based simulator to execute models and analyze their performance.

Mots clés: System on chip; Hardware/software co-design; UML; Shared resources modeling; Architecture exploraition

Domaines: Sciences de l'ingénieur [physics]

Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Renaud Pacalet. Shared resources high-level modeling in embedded systems using virtual nodes. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference 2009, Jun 2009, Toulouse, France. ⟨10.1109/NEWCAS.2009.5290506⟩. ⟨hal-00423997⟩