Flexible architectures for LDPC decoders based on network on chip paradigm

Fabrizio Vacca (1) , Guido Masera (1) , Hazem Moussa (2, 3) , Amer Baghdadi (2, 3) , Michel Jezequel (2)

1 Polito - Politecnico di Torino = Polytechnic of Turin
2 ELEC - Département Electronique
3 Lab-STICC_TB_CACS_IAS

This paper explores the possibility of building a flexible Low Density Parity Check (LDPC) decoder using a Network On Chip communication infrastructure. Even if this idea is not completely new, previously published works suffered from an excessive area occupation and their practical impact has been very limited. In the following we analyze two possible NOCs specifically designed for the LDPC case. From synthesis results it can be observed how the proposed networks outperform previous implementations in terms of active area with no significant bandwidth loss. Finally to prove the effectiveness of the proposed approach a complete, partially parallel LDPC decoder design is resented and characterized in terms of throughput and area occupation.

Mots clés: Network on chip; LDPC; Channel decoder; Multiprocessor SOC

Domaines: Electronique

Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jezequel. Flexible architectures for LDPC decoders based on network on chip paradigm. DSD 2009 : 12th Euromicro Conference on Digital System Design, Sep 2009, Patras, Greece. ⟨hal-00423917⟩