Synthesis of property monitors for online fault detection

Abstract : An original method for generating components that capture the occurrence of events is proposed, and logical and temporal properties of hardware/software embedded systems are monitored. The properties are written in PSL, under the form of assertions in declarative form. The method includes the construction of a library of primitive digital components for the PSL temporal and sequence operators. These building blocks are interconnected to construct complex properties, resulting in a synthesizable digital module that can be properly linked to the digital system under scrutiny.
Keywords : PSL hardware
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Contributor : Lucie Torella <>
Submitted on : Wednesday, September 23, 2009 - 2:22:10 PM
Last modification on : Monday, July 8, 2019 - 3:10:26 PM




K. Morin-Allory, E. Gascard, D. Borrione. Synthesis of property monitors for online fault detection. Journal of Circuits, Systems, and Computers (JCSC), 2007, 16 (6), pp.943 - 960. ⟨10.1142/S0218126607004088⟩. ⟨hal-00419356⟩



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