Comparing Transient-Fault Effects on Synchronous and on Asynchronous Circuits

Rodrigo Possamai Bastos (1, 2) , Y. Monnet (3) , G. Sicard (1) , Fernanda Lima Kastensmidt (2) , Marc Renaudin (3) , Ricardo Reis (2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 UFRGS - Universidade Federal do Rio Grande do Sul [Porto Alegre]
3 Tiempo SAS [Montbonnot Saint Martin]

A methodology to evaluate transient-fault effects on synchronous and asynchronous is presented in this work. It is developed by means of fault-injection simulation campaigns on gate-level circuit implementations. The methodology is able to deal with the particularities of asynchronous circuits. Unlike previous works, it permits to compare the sensitivity of circuits designed by synchronous and asynchronous logics. The resultant metrics allow identifying at high-level abstraction what is the logic that makes the circuit more transient-fault sensitive. As a case study, a crypto-processor in versions synchronous and asynchronous was evaluated.

Mots clés: transient-faults; asynchronous circuits

Domaines: Micro et nanotechnologies/Microélectronique

Rodrigo Possamai Bastos, Y. Monnet, G. Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, et al.. Comparing Transient-Fault Effects on Synchronous and on Asynchronous Circuits. 15th IEEE International On-Line Testing Symposium (IOLTS'09), Jun 2009, Sesimbra-Lisbon, Portugal. pp.29-34, ⟨10.1109/IOLTS.2009.5195979⟩. ⟨hal-00419061⟩