Automatic phase detection for stochastic on-chip traffic generation

Abstract : During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently done using traffic generators which emulate the SoC components (IPs) behavior: processors, hardware accelerators, etc. Traffic generated by processor-like IPs is highly non-regular, it must be decomposed into program phases. We propose an original feature for NoC prototyping, inspired by techniques used in processor architecture performance evaluation: the automatic detection of traffic phases. Integrated in our NoC prototyping environment, this feature permits to have a completely automatic toolchain for the generation of stochastic traffic generators. We show that our traffic generators emulate precisely the behavior of processors and that our environment is a versatile tool for networks-on-chip prototyping. Simulations are performed in a SystemC-based simulation environment with a mesh network-on-chip (DSPIN) and a processor running MP3 decoding applications.
Type de document :
Communication dans un congrès
International Conference on Hardware Software Codesign (isss 06), 2006, Seoul, South Korea. pp.88 - 93, 2006
Liste complète des métadonnées

https://hal.archives-ouvertes.fr/hal-00410758
Contributeur : Tanguy Risset <>
Soumis le : lundi 24 août 2009 - 12:08:27
Dernière modification le : samedi 27 octobre 2018 - 01:19:53

Identifiants

  • HAL Id : hal-00410758, version 1

Citation

Tanguy Risset, Antoine Fraboulet, Antoine Scherrer. Automatic phase detection for stochastic on-chip traffic generation. International Conference on Hardware Software Codesign (isss 06), 2006, Seoul, South Korea. pp.88 - 93, 2006. 〈hal-00410758〉

Partager

Métriques

Consultations de la notice

183