On-chip Processor Traffic Modeling for NoC Design

Tanguy Risset 1, 2 Antoine Fraboulet 3 Antoine Scherrer 4
2 SWING - Smart Wireless Networking
Inria Grenoble - Rhône-Alpes, CITI - CITI Centre of Innovation in Telecommunications and Integration of services
3 AMAZONES - Ambient Middleware Architectures: Service-Oriented, Networked, Efficient and Secured
CITI - CITI Centre of Innovation in Telecommunications and Integration of services, Inria Grenoble - Rhône-Alpes
Abstract : We propose a chapter focused on multi-processor system on chip (MPSoC) traffic modeling for embedded computing systems (telecommunication and multimedia mainly). The chapter will be based on the knowledge acquired during the PhD of Antoine Scherrer [4] entitled "Statistical analysis of on chip communications". Our experience shows that, while it is possible to emulate quite precisely the traffic generated by a dedicated ip, it is much more difficult to emulate the traffic produced by processors associated with caches. Hence, we will concentrate on the efficient analysis and synthesis on on-chip traffic generated by processors ip. We will review the dierent techniques used for NoC traffic modeling and we will insist on two points for future traffic generators: the use of advanced statistical models (i.e. second order statistics) and the use of multi-phase trac (i.e. piece-wise stationary models). The chapter will be illustrated by performance results of a multi-phase trac generator used in a cycle accurate MPSoC simulator based on systemC [2].
Type de document :
Chapitre d'ouvrage
CRC Press, Taylor and Francis Group. Networks-on-Chips: Theory and Practice, CRC Press, pp.95-122, 2009
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https://hal.archives-ouvertes.fr/hal-00410688
Contributeur : Tanguy Risset <>
Soumis le : lundi 24 août 2009 - 10:19:41
Dernière modification le : samedi 27 octobre 2018 - 01:20:09

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  • HAL Id : hal-00410688, version 1

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Tanguy Risset, Antoine Fraboulet, Antoine Scherrer. On-chip Processor Traffic Modeling for NoC Design. CRC Press, Taylor and Francis Group. Networks-on-Chips: Theory and Practice, CRC Press, pp.95-122, 2009. 〈hal-00410688〉

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