S. Guilley, S. Chaudhuri, L. Sauvage, T. Graba, J. Danger et al., Vinh-Nga Vong, and Maxime Nassar. Place-and-Route Impact on the Security of DPL Designs in FPGAs, HOST, IEEE, pp.29-35, 2008.

S. Guilley, L. Sauvage, J. Danger, N. Selmane, and R. Pacalet, Silicon-level solutions to counteract passive and active attacks. In FDTC, 5th Workshop on Fault Detection and Tolerance in Cryptography, IEEE- CS, pp.3-17, 2008.
DOI : 10.1109/fdtc.2008.18
URL : https://hal.archives-ouvertes.fr/hal-00311431

T. Le, C. Canovas, and J. Ere, An overview of side channel analysis attacks, Proceedings of the 2008 ACM symposium on Information, computer and communications security , ASIACCS '08, pp.33-43, 2008.
DOI : 10.1145/1368310.1368319

P. Kocher, J. Jaffe, and B. Jun, Differential Power Analysis, Proceedings of CRYPTO'99, pp.388-397, 1999.
DOI : 10.1007/3-540-48405-1_25

D. Suzuki and M. Saeki, Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style, CHES, pp.255-269, 2006.
DOI : 10.1007/11894063_21

K. Tiri and I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.246-251, 2004.
DOI : 10.1109/DATE.2004.1268856