Hardware wrapper classification and requirements for on-chip interconnects.

Abstract : The new SoC paradigms brought on-chip interconnections in foreground. In order to achieve more reuse, flexibility, and performance, bus based interconnections are no more sufficient. The link between IP blocks and interconnections, the transport layer of the OSI reference model, enable a clean separation of computation and communication. As far as we know, no study has been yet performed on a customisable transport layer according to both interconnection and application. This paper propose some requirements that will have to be taken into account while designing hardware wrappers, and a classification of the services such a wrapper can implement.
Type de document :
Communication dans un congrès
Signaux, Circuits et Systèmes, 2004, Monastir, Tunisia. pp.4, 2004
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https://hal.archives-ouvertes.fr/hal-00399633
Contributeur : Antoine Fraboulet <>
Soumis le : samedi 27 juin 2009 - 10:40:25
Dernière modification le : samedi 27 octobre 2018 - 01:20:21

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  • HAL Id : hal-00399633, version 1

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Antoine Scherrer, Antoine Fraboulet, Tanguy Risset. Hardware wrapper classification and requirements for on-chip interconnects.. Signaux, Circuits et Systèmes, 2004, Monastir, Tunisia. pp.4, 2004. 〈hal-00399633〉

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