Process Optimization for High Temperature SiC Lateral Devices

Maher Soueidan (1) , Mihai Lazar (1) , Duy Minh Nguyen , Dominique Tournier (1) , Christophe Raynaud (1) , Dominique Planson (1)

1 AMPERE - Ampère

Complementary lateral structures, N-JFETs. P-JFETS and bipolar diodes, have been implemented in p and n-type 4H-SiC wafers with epilayers. The device were optimized using finite element code MEDICI (TM) simulations, based oil ion implanted and etched Reduced-Surface-Field structures. Two Ti/Ni alloy composition are found to form ohmic contacts compatibles with high temperature device operation. 900 degrees C and respectively 1000 degrees C post-metallisation annealing during 2min are necessary. The presence of a graphite layer is determined by XPS (X-ray photon spectroscopy) analyses at the metal-semiconductor interface. Oil the fabricated p and n-type lateral JFETs in blocking state, breakdown voltage as high as 600V are obtained.

Mots clés: RESURF; LJFETs; Ti/Ni ohmic contacts; high temperature

Domaines: Energie électrique

Maher Soueidan, Mihai Lazar, Duy Minh Nguyen, Dominique Tournier, Christophe Raynaud, et al.. Process Optimization for High Temperature SiC Lateral Devices. CSCRM, Sep 2008, Barcelone, Spain. pp.585-588, ⟨10.4028/www.scientific.net/MSF.615-617.585⟩. ⟨hal-00391358⟩