Optimized Decimation Filter Architecture for 5th Order Σ∆ Converter in GSM/ UMTS/ Wi-max Radio Receiver

Abstract : This paper presents an efficient design of a decimation filter for a continuous-time (CT) complex lowpass ΣΔ modulator in Multi-standards receiver. The proposed architecture meets the requirements of three standards: Wi-max, UMTS and GSM. The optimization of the proposed decimation structure leads to three implementation architectures which optimized in different ways : area (in terms of used resources) and power consumption for the required thruoghtput. Experimental results illustrate the high-speed data throughput and low-power consumption features of the proposed designs.
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https://hal.archives-ouvertes.fr/hal-00389913
Contributor : Bertrand Le Gal <>
Submitted on : Saturday, May 30, 2009 - 9:14:48 AM
Last modification on : Thursday, January 11, 2018 - 6:21:09 AM

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  • HAL Id : hal-00389913, version 1

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M. Jebalia, C. Rebai, Bertrand Le Gal, Dominique Dallet. Optimized Decimation Filter Architecture for 5th Order Σ∆ Converter in GSM/ UMTS/ Wi-max Radio Receiver. IEEE International conference on Signals, Circuits & Systems (SCS'08), Dec 2008, Hammamet, Tunisia. pp.000. ⟨hal-00389913⟩

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