Low Power Decimation and Channel Selection Filter for Multistandard Receiver

Abstract : This work presents a low-power multistandard decimation and channel selection filter architecture. The filter is suitable after an over-sampling sigma-delta converter and performs decimation in two stages. The first stage is a modified structure of the Cascade of Integrators-Combs (CIC) filter and allows reducing sampling rate downto only the double of the Nyquist frequency. The second stage composed of classical FIR filter, has relaxed specifications and performs channel selection. Implementation of the proposed filter for UMTS and GSM standards shows good filtering performances. The signal to ratio measured for UMTS is 14,65 dB and for GSM 26,96 dB which satisfy largely the standards requirements. Implementation on ASIC 65-nm process technology shows power consumption gain of 14% in comparison to previously proposed low-power architecture.
Complete list of metadatas

https://hal.archives-ouvertes.fr/hal-00389865
Contributor : Bertrand Le Gal <>
Submitted on : Friday, May 29, 2009 - 9:46:38 PM
Last modification on : Thursday, January 11, 2018 - 6:21:08 AM

Identifiers

  • HAL Id : hal-00389865, version 1

Citation

N. Khouja, K. Grati, A. Ghazel, Bertrand Le Gal. Low Power Decimation and Channel Selection Filter for Multistandard Receiver. IEEE Wireless Communications and Wireless Networking Conference (WCNC'09), 2009, Budapest, Hungary. pp.000. ⟨hal-00389865⟩

Share

Metrics

Record views

72