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ESD Induced Latent Defects In CMOS ICs And Reliability Impact

Abstract : A dedicated test vehicle was designed to study the impact of ESD induced latent defects on digital and analog CMOS circuits. Both CDM and TLP stresses were applied to these circuits through a specific pad which allows stressing the circuit core. Both electrical characterization and non-destructive failure analysis were performed to locate the induced defect. For digital circuits, functionality is not affected although the IDDQ quiescent current increased. However, after burn-in and storage, it was observed that the IDDQ current significantly increased suggesting that the circuit lifetime is degraded. In contrast, even at very low stress level, the analog circuit exhibits a dramatic offset degradation and no recovery is observed after burn-in.
keyword : ESD latent defect CDM
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Submitted on : Tuesday, May 19, 2009 - 10:21:00 PM
Last modification on : Tuesday, October 19, 2021 - 11:16:24 PM
Long-term archiving on: : Thursday, June 10, 2010 - 7:30:17 PM


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  • HAL Id : hal-00385694, version 1


Nicolas Guitard, David Trémouilles, Stéphane Alves, Marise Bafleur, Félix Beaudoin, et al.. ESD Induced Latent Defects In CMOS ICs And Reliability Impact. Electrical Overstress and Electrostatic Discharge (EOS/ESD) Symposium, Sep 2004, Dallas, United States. pp.174-181. ⟨hal-00385694⟩



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