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High Efficiency Reconfigurable Cache for Image Processing

Abstract : System On Chip designs commonly use high performance data processing engines able to execute hardwired algorithms. While the performance of these engines heavily relies on the bandwidth of accesses to external memories, traditional cache architectures and algorithms suffer a lack of effectiveness for highly structured data like in 2D or 3D image processing. In a previous work, Mancini and Eveno proposed the nD-AP Cache (n-Dimensional Adaptive and Predictive Cache) in order to target multidimensional data processing. It has been shown that this cache is efficient for applications where data fetches are performed based on the history of data values. Although, the performance depends strongly on the way that the nD-AP Cache running parameters are tuned, no predefined methodology to set these parameters has been proposed before. In this paper, we study the parameters tuning aspect. Then, we compare the efficiency of the nD-AP Cache to three associative caches. Numerical results indicate that 100% improvement in run time performance can be achieved while keeping relatively low hardware cost.
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Contributor : Zahir Larabi <>
Submitted on : Monday, May 18, 2009 - 9:59:43 AM
Last modification on : Thursday, November 19, 2020 - 1:01:01 PM
Long-term archiving on: : Thursday, June 10, 2010 - 9:28:59 PM


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  • HAL Id : hal-00384989, version 1


Zahir Larabi, Yves Mathieu, Stéphane Mancini. High Efficiency Reconfigurable Cache for Image Processing. ERSA'2009, Jul 2009, Las Vegas USA, United States. pp.226-232. ⟨hal-00384989⟩



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