Verification of Timed Automata via Satisfiability Checking

Peter Niebert (1) , Moez Mahfoudh (2) , Eugene Asarin (2) , Marius Bozga (2) , Oded Maler (2) , Navendu Jain (3)

1 LIF - Laboratoire d'informatique Fondamentale de Marseille - UMR 6166
2 VERIMAG - IMAG - VERIMAG
3 Computer Science and Eng. Dept.

In this paper we show how to translate bounded-length verification problems for timed automata into formulae in difference logic, a propositional logic enriched with timing constraints. We describe the principles of a satisfiability checker specialized for this logic that we have implemented and report some preliminary experimental results.

Mots clés: timed automata; bounded model-checking; satisfiability checking; difference logic

Domaines: Systèmes embarqués

Peter Niebert, Moez Mahfoudh, Eugene Asarin, Marius Bozga, Oded Maler, et al.. Verification of Timed Automata via Satisfiability Checking. Formal Techniques in Real-Time and Fault-Tolerant Systems 7th International Symposium, FTRTFT 2002, Sep 2002, Oldenburg, Germany. pp.225-244, ⟨10.1007/3-540-45739-9⟩. ⟨hal-00374806⟩