Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2008

Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA

Eric Senn
Johann Laurent
Jean-Philippe Diguet
Fichier non déposé

Dates et versions

hal-00370823 , version 1 (25-03-2009)

Identifiants

  • HAL Id : hal-00370823 , version 1

Citer

Eric Senn, Johann Laurent, Jean-Philippe Diguet. Multi-Level power consumption modelling in the AADL design flow for DSP, GPP, and FPGA. International Workshop on Model Based Architecting and Construction of Embedded Systems (ACESMB 2008, in conjunction with MODELS 2008), Sep 2008, Toulouse, France. pp.1. ⟨hal-00370823⟩
85 Consultations
0 Téléchargements

Partager

Gmail Facebook X LinkedIn More