Alper Buyuktosunoglu , and Sandhya Dwarkadas. A dynamically tunable memory hierarchy, IEEE Transactions on Computers, 2003. ,
The Theory & Practice of 3D PET, 1998. ,
DOI : 10.1007/978-94-017-3475-2
Chidamber Kulkarn, and al. Data Access and Storage Management for Embedded Programmable Processors, 2002. ,
An efficient texture cache for programmable vertex shaders, IEEE ISCAS, 2006. ,
Exploiting cache in multimedia. Multimedia Computing and Systems, IEEE International Conference on, pp.345-350, 1999. ,
Exploiting cache in multimedia. Multimedia Computing and Systems, IEEE International Conference on, pp.345-350, 1999. ,
Improving data prefetching efficacy in multimedia applications, Multimedia Tools and Applications, pp.159-178, 2003. ,
A coprocessor for real-time mpeg4 facial animation on mobiles, Proc. of ESTIMedia, 2003. ,
Intel smart memory access: Minimizing latency on intel coretm microarchitecture, Technology @Intel Magazine, 2006. ,
DOI : 10.1109/hotchips.2006.7477876
Hierarchical partitioning for piecewice linear algorithms, Proceedings of the International Symposium on PARELEC, pp.153-160, 2006. ,
Stride directed prefetching in scalar processors. Microarchitecture, 1992. MICRO 25, Proceedings of the 25th Annual International Symposium on, pp.102-110, 1992. ,
Prefetching using Markov predictors, IEEE Transactions on Computers, vol.48, issue.2, pp.121-133, 1999. ,
DOI : 10.1109/12.752653
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.637.7652
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Computer Architecture Proceedings. 17th Annual International Symposium on, pp.364-373, 1990. ,
Data cache and direct memory access in programming mediaprocessors, IEEE Micro, vol.21, issue.4, pp.33-42, 2001. ,
DOI : 10.1109/40.946678
A novel systemon-chip architecture for efficient image processing, Rapid System Prototyping The 19th IEEE/IFIP International Symposium on, pp.165-171, 2008. ,
A reconfigurable multilevel parallel texture cache memory with 75-gb/s parallel cache replacement bandwidth Computer Architecture: A Quantitative Approach, IEEE Journal of Solid-State Circuits, 1996. ,
Reducing conflicts in directmapped caches with a temporality-based design. Parallel Processing, Proceedings of the 1996 International Conference on, pp.154-163, 1996. ,
General-purpose processor huffman encoding extension Information Technology: Coding and Computing, Proceedings. International Conference on, pp.158-163, 2000. ,
DOI : 10.1109/itcc.2000.844200
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.32.2981