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Efficient data access management for FPGA-Based image processing SoCs

Abstract : In this paper, we propose a low-cost n-dimensional cache (nD-Cache) architecture for FPGA-Based image and signal processing Systems On Chip (SoCs). The architecture allows efficient access to structured data as in 2D or 3D images. We developed a theoretical model for our architecture. It gives a methodology to define cache's practical implementation based on the application and system parameters. Complexity and performance measurements for selected image processing algorithms like jumping snake and 2D Back-Projection are done and compared to classical solutions like associative caches. The architecture is shown to be efficient for tracking algorithm applications by exploiting spacial and temporal locality. Numerical results indicate that 50% improvement in run-time performance can be achieved.
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Contributor : Zahir Larabi <>
Submitted on : Thursday, April 9, 2009 - 2:13:59 PM
Last modification on : Thursday, November 19, 2020 - 1:01:01 PM
Long-term archiving on: : Thursday, June 30, 2011 - 11:18:04 AM


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  • HAL Id : hal-00368532, version 2


Zahir Larabi, Yves Mathieu, Stéphane Mancini. Efficient data access management for FPGA-Based image processing SoCs. 20th IEEE/IFIP International Symposium on Rapid System Prototyping (RSP\'2009), Jun 2009, Paris, France. pp.159-165. ⟨hal-00368532v2⟩



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